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Home » Seminar » Seminar Topics

Clockless Chips

Expert Suggestions on Preparation for Computer Based CAT-09
Seminar

  • Clock speeds are now in the gigahertz range and there is not much room for speedup before physical realities start to complicate things. With gigahertz clock powering a chip, signals barely have enough time to make it across the chip before the next clock tick. At this point, speeding up the clock frequency could become disastrous. This is where a chip that is not constricted by clock comes in to action.

    Clockless approach, which uses a technique known as asynchronous logic, differs from conventional computer circuit design in that the switching on and off of digital circuits is controlled individually by specific pieces of data rather than by a tyrannical clock that forces all of the millions of the circuits on a chip to march in unison.

    A major hindrance to the development of the clockless chips is the competitiveness of the computer industry. Presently, it is nearly impossible for companies to develop and manufacture a Clockless chip while keeping the cost reasonable. Another problem is that there aren�t much tools used to develop asynchronous chips. Until this is possible, Clockless chips will not be a major player in the market.

    In this seminar the topics covered are � general concept of asynchronous circuits, their design issues and types of design. The major designs discussed are Bounded delay method, Delay insensitive method & the Null Conventional Logic (NCL).

    The seminar also does a comparison of synchronous and asynchronous circuits and the applications in which asynchronous circuits are used.

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